The Wintersweet W86 CPU ISA

I am interested in instruction set design mainly because of my dream of being a historian (well, one that does not need to worry about money). I imagine if I would go back to the end of 60's with my knowledge of the computer history, what I would say to Ken Olsen to get the instruction set design right, and to get the strategy of implementing it right?

I have studied various ISA designs and their levels of success in history. I imagine that the desirable ISA should be expandable and shrinkable, down to 8 bit to compete with micros, and up to 64bit for the new millenium, with a focus on 16 bit in the 70's and 32 bit in the 80's, that all be backward compatible on machine code level. It should be able to survive the RISC hey days and regain speed crown in the 90's. It should not introduce features that are difficult to implement with pipelines or superscalar execution. It should be prepared for the cache bottleneck. When searching the internet about ISA's I found this post to be most interesting.

I think the X86 ISA is attractive regarding to my requirements. I twick it a little bit to avoid some if its historical mistakes, and call the result W86 ISA. I imagine DEC would implement its 16 bit version instead of PDP11, get out its 8 bit version to compete with micros, and implement its 32 bit version instead of VAX. The history would have been vastly different.

8 bit guide lines: 64KB address range; 16 bit base registers, 8 bit index registers and accumulater. Computation is done between register and memory.

16 bit guide lines: 1MB address range; 24 bit base registers, 16 bit index registers and accumulator. Binary level backward compatibility is important.

32 bit guide lines: 4GB address range; 16 general purpose 32bit registers. Backward compatibility. Assembly level backward compatibility is important.

64 bit guide lines: 16 general purpose 64 bit registers.

Instruction Guide Lines
Instruction Design

One Byte Opcodes
Needs some b/w/dw/qw pack/unpack instructions

XXH X0H X1H X2H X3H X4H X5H X6H X7H X8H X9H XAH XBH XCH XDH XEH XFH

0XH ADD
Eb,Gb ADD
Ev,Gv ADD
Gb,Eb ADD
Gv,Ev SHL
Eb,Gb SHL
Ev,Gb SHR
Eb,Gb SHR
Ev,Gb OR
Eb,Gb OR
Ev,Gv OR
Gb,Eb OR
Gv,Ev MOV
Eb,Gb MOV
Ev,Gv MOV
Gb,Eb MOV
Gv,Ev

1XH ADC
Eb,Gb ADC
Ev,Gv ADC
Gb,Eb ADC
Gv,Ev SAL
Eb,Gb SAL
Ev,Gb SAR
Eb,Gb SAR
Ev,Gb SBB
Eb,Gb SBB
Ev,Gv SBB
Gb,Eb SBB
Gv,Ev CVT
Eb,Gb CVT
Ev,Gv CVT
Gv,Eb CVT
Gv,Ev

2XH AND
Eb,Gb AND
Ev,Gv AND
Gb,Eb AND
Gv,Ev ROL
Eb,Gb ROL
Ev,Gb ROR
Eb,Gb ROR
Ev,Gb SUB
Eb,Gb SUB
Ev,Gv SUB
Gb,Eb SUB
Gv,Ev TEST
Eb,Gb TEST
Ev,Gv MVZX
Gv,Eb MVZX
Gv,Ev

3XH IMUL
Eb,Gb IMUL
Ev,Gv IMUL
Gb,Eb IMUL
Gv,Ev BSF
Eb,Gb BSF
Ev,Gb BSR
Eb,Gb BSR
Ev,Gb CMP
Eb,Gb CMP
Ev,Gv CMP
Gb,Eb CMP
Gv,Ev XCHG
Eb,Gb XCHG
Ev,Gv MVSX
Gv,Eb MVSX
Gv,Ev

4XH IMUL
Gv,Ev IMUL
Ev,Gv MUL
Gv,Ev MUL
Ev,Gv IDIV
Gv,Ev IDIV
Ev,Gv DIV
Gv,Ev DIV
Ev,Gv BT
Ev,Gv BTC
Ev,Gv BTR
Ev,Gv BTS
Ev,Gv

5XH GRP#1
Eb,Ib GRP#1
Ev,Ib GRP#1
Eb,Ib GRP#1
Ev,Iv GRP#2
Eb,Ib GRP#2
Ev,Ib GRP#2
Eb,1 GRP#2
Ev,1 GRP#3
Eb,Ib GRP#3
Ev,Ib GRP#3
Eb,Ib GRP#3
Ev,Iv GRP#4
Eb GRP#4
Ev GRP#5
Gb,Ib GRP#5
Gv,Iv

6XH JS
Jb JNS
Jb JP
Jb JNP
Jb JL
Jb JNL
Jb JLE
Jb JNLE
Jb JS
Jv JNS
Jv JP
Jv JNP
Jv JL
Jv JNL
Jv JLE
Jv JNLE
Jv

7XH JO
Jb JNO
Jb JB
Jb JNB
Jb JZ
Jb JNZ
Jb JBE
Jb JNBE
Jb JO
Jv JNO
Jv JB
Jv JNB
Jv JZ
Jv JNZ
Jv JBE
Jv JNBE
Jv

8XH PUSH
EAX PUSH
ECX PUSH
EDX PUSH
EBX PUSH
ESP PUSH
EBP PUSH
ESI PUSH
EDI POP
EAX POP
ECX POP
EDX POP
EBX POP
ESP POP
EBP POP
ESI POP
EDI

9XH INC
EAX INC
ECX INC
EDX INC
EBX INC
ESP INC
EBP INC
ESI INC
EDI CLR
EAX CLR
ECX CLR
EDX CLR
EBX CLR
ESP CLR
EBP CLR
ESI CLR
EDI

AXH CMP
EAX,Ib CMP
ECX,Ib CMP
EDX,Ib CMP
EBX,Ib CMP
ESP,Ib CMP
EBP,Ib CMP
ESI,Ib CMP
EDI,Ib CMP
EAX,Iv CMP
ECX,Iv CMP
EDX,Iv CMP
EBX,Iv CMP
ESP,Iv CMP
EBP,Iv CMP
ESI,Iv CMP
EDI,Iv

BXH REX REX REX REX REX REX REX REX REX REX REX REX REX REX REX REX

CXH ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC

DXH ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC

EXH INT3 INT
Ib INTO IRET JMP JMP JMP CALL CALL RET RET RET
Iw RET
Iw

FXH PRE-
COND PRE-
NNR IN OUT CLC STC CLI STI CLD STD LOCK NOP

PRE-NNR: NEG if ADD,ADC,SUB,SBB; NOT if AND,OR,NOR; With C if shift/roll
PRE-COND: Updates BRANCH state bits (Test,CMP updates BRANCH state bits by default)
REX: XXXXWRXB; extension bits for operandSize,REG,indexREG,baseREG
GRP#1: ADD,ADC,SUB,SBB,AND,OR,IMUL,CMP
GRP#2: SHL,SHR,SAL,SAR,ROL,ROR
GRP#3: MOV,CVT,TEST,MVZX,XCHG,MVSX
GRP#4: INC,DEC,NOT,NEG,JUMP,CALL,PUSH
GRP#5: IMUL,MUL,IDIV,DIV,BT,BTC,BTR,BTS
0XH-3XH: Operations with two operands; REG--R/M or R/M--REG
4XH: REX prefix
5XH: Operations with R/M and immediates
6XH-7XH: Branches
8XH-BXH: PUSH,POP and short cuts operations
CXH-DXH: Floating point instructions
EXH-FXH: Misc instructions
Need: BT,BTC,BTR,BTS using register index